1. Field of the Invention
The present invention relates to: a small circuit device in which a lead electrically connected to a circuit element built therein is exposed to the outside from a side surface of a sealing resin; and a method for manufacturing the same.
2. Description of the Related Art
The capacitance of semiconductor devices is increasing year after year, which in turn increases the number of lead terminals to work as various signal lines. Along with this trend, a semiconductor device with a quad flat package (QFP) with lead terminals extending in four directions and a semiconductor device with a quad flat non-leaded (QFN) package have been increasingly used. Meanwhile, small, thin and light semiconductor devices are demanded for use in cellular phones, portable computers, and the like. For this reason, there is a demand for downsizing of the mounting area for a semiconductor device, and a chip size package (CSP) is utilized to meet this demand. The CSP is a type of package mountable in an area equal to or slightly larger than its chip size by having leads exposed from the back surface of a resin sealed body.
As a conventional semiconductor-device manufacturing method in which a resin is molded in a resin-sealing die with a sealing sheet, there is a known technology in which: the sealing sheet is pasted on a lead frame at an entire surface opposed to the surface to which a semiconductor element is fixed; the lead frame pasted with the sealing sheet is placed in the resin-sealing die; and the resin is molded. This technology is described for instance in Japanese Patent Application Publication No. 2004-172542.
Hereinafter, the semiconductor-device manufacturing method will be described with reference to FIGS. 10 to 12. FIG. 10 is a cross-sectional view for describing a lead frame pasted with a sealing sheet. FIG. 11 is a cross-sectional view for describing a state where the lead frame is placed in a resin-sealing die. FIG. 12 is a cross-sectional view for describing a state after a resin package is formed.
Firstly, as shown in FIG. 10, multiple mount portions 111 are formed inside a lead frame 101, each mount portion 111 including at least a signal-connecting terminal 102 and a die pad 103 on which a semiconductor chip 104 is mounted. After a sealing sheet 106 is pasted on the back surface of the lead frame 101, the semiconductor chip 104 is bonded to the upper surface of the die pad 103 with an adhesive. Then, the semiconductor chip 104 bonded to the die pad 103 is electrically connected to the signal-connecting terminal 102 through a thin metal wire 105.
Subsequently, as shown in FIG. 11, the lead frame 101 which is pasted with the sealing sheet 106 and which is connected to the semiconductor chip 104 is placed in a cavity 109 of a resin-sealing die including an upper die 107 and a lower die 108. At this point, end portions of the lead frame 101 and of the sealing sheet 106 are held between the upper die 107 and the lower die 108, thereby forming the cavity 109. Then, although unillustrated, a sealing resin is injected into the resin-sealing die through a resin injection gate provided therein, and the resin is molded.
Thereafter, as shown in FIG. 12, the resin-sealing die is filled with the sealing resin, and a resin package 110 is formed. After that, the lead frame 101 in which the common resin package 110 is formed is taken out from the resin-sealing die. Then, although unillustrated, the common resin package 110 is cut off by dicing into the individual mount portions 111, and thus semiconductor devices are completed.
In the semiconductor device with the above-described configuration, the lower surface and a side surface of the signal-connecting terminal 102 are exposed to the outside. Solder is attached to this exposed portion of the signal-connecting terminal 102, and the semiconductor device is mounted thereon. However, if the semiconductor chip 104 having as many as several tens of electrodes is formed in a small package, the individual signal-connecting terminals 102 are down-sized. Accordingly, the area of each signal-connecting terminal 102 exposed to the outside is narrowed, which also reduces the area where the signal-connecting terminal 102 is in contact with a brazing filler material used for connection. This results in a problem of poor connection reliability in a semiconductor element mounted with the brazing filler material.
Furthermore, in the above-described method for manufacturing a semiconductor device, the signal-connecting terminal 102 of each mount portion 111 is integrally supported by a tie bar formed between two mount portions 111. However, if the width of each formed signal-connecting terminal 102 decreases along with the increase in the pin count of the semiconductor chip 104, it is difficult to ensure sufficient connection strength between the signal-connecting terminal 102 and the tie bar. This leads to a problem that the signal-connecting terminal 102 connected to the tie bar is deformed in the middle of the manufacturing process.